A static RAM (SRAM) does not need to be refreshed like a DRAM (Dynamic Random Access Memory) and therefore operates at a high-speed and is used as a high-speed memory.
On the other hand, in recent years, a reduction in power consumption of a memory has been demanded. In order to realize a memory with lower power consumption, it is preferable to reduce the operating voltage. In a DRAM, if the operating voltage is reduced, the charge voltage of a capacitor provided in a memory cell is reduced, and therefore, it is preferable to perform the refresh operation frequently, and therefore, there is a problem that it is difficult to reduce power consumption. As a result, the power consumption is reduced by reducing the operating voltage of an SRAM.
A normal SRAM has a plurality of word lines and a plurality of pairs of bit lines arranged so as to be perpendicular to each other, a plurality of static memory cells arranged in correspondence to the intersections of the plurality of word lines and the plurality of pairs of bit lines, a plurality of column circuits arranged in correspondence to each pair of bit lines, a row decoder, a column decoder, a word line driver, and a plurality of column switches. Each column circuit has a sense amplifier, a precharge circuit, an equalizer, a keeper circuit, a pair of bit lines separation switch, etc.
FIG. 1 is a diagram illustrating a configuration of a portion corresponding to one pair of bit lines, i.e., one column of a general SRAM. Such a circuit is arranged in the number of sets of pairs of bit lines.
As illustrated in FIG. 1, the SRAM has a plurality (n+1) of word lines WL0 to WLn extending in parallel in the transverse direction, a pair of bit lines BL and BLX extending in parallel in the vertical direction, a plurality (n+1) of static memory cells C0 . . . Cn arranged in correspondence to the intersections of the plurality of word lines and the pair of bit lines, a pair of extended bit lines RD and RXD provided in correspondence to the pair of bit lines BL and BLX, transistors Tr and TrX forming a connection circuit of the pair of bit lines BL and BLX and the pair of extended bit lines RD and RDX, a precharge circuit PC and a keeper circuit KP connected between the pair of bit lines BL and BLX, and a sense amplifier SA and an equalizer EQ connected between the pair of extended bit lines RD and RDX.
Each memory is a well-known static memory cell having a flip-flop in which the inputs and outputs of two inverters are connected mutually and two transistors provided between two connection nodes of the flip-flop and the pair of bit lines BL and BLX. The gates of the two transistor are connected to the corresponding word line WL and when a row selection signal is applied to the word line, the transistor is brought into conduction (turned on) and a state is brought about where the memory cell is connected to the pair of bit lines BL and BLX.
The pair of bit lines BL and BLX is very long and to which a number (N+1) of the memory cells C0 . . . Cn are connected. The precharge circuit PC operates when a precharge signal PRE turns to “Low (L)” and precharges the pair of bit lines BL and BLX to “High (H)” level and does not operate when PRE is at H (off state). The keeper circuit KP maintains the bit line on the H side of the pair of bit lines BL and BLX at H. The transistors Tr and TrX are brought into conduction when a column signal COL is at L and brought into a cut-off state when the column signal COL is at H. The sense amplifier SA enters the operating state when a sense amplifier start signal SAE is at H and amplifies one of the pair of bit lines BL and BLX which is on the high voltage side to H and the other on the low voltage side to L and does not operate when SAE is at L (off state). The equalizer EQ has the same configuration as that of the precharge circuit PC and brings the pair of bit lines BL and BLX into the H state by short-circuiting them when an equalize signal EQD is at L and does not operate when the equalize signal EQD is at H (off state).
FIG. 2 is a time chart illustrating the read operation of the SRAM illustrated in FIG. 1. Here, WL0 represents a row selection signal to be applied to the word line WL0 in the zeroth row, BL/BLX represent voltages of the pair of bit lines BL and BLX, and RD/RDX represent voltages of the pair of extended bit lines RD and RDX, respectively.
As described above, to the pair of bit lines BL and BLX, a number (n+1) of memory cells are connected and to the word line WL of one the memory cells (in the zeroth row), the row selection signal (active at H) is applied, and thus, the two transistors are brought into conduction. In response to this, the voltage of one of the pair of bit lines BL and BLX drops in accordance with the stored data of the memory cell. At this time, the column signal COL is at L, the transistors Tr and TrX are in the conduction state, and therefore, the pair of extended bit lines RD and RDX also changes in the same way as that of the pair of bit lines BL and BLX.
On the other hand, the precharge signal PRE and the equalize signal EQD are at H and the precharge circuit PC and the equalizer EQ enter the off state. The sense amplifier start signal SAE is at L and the sense amplifier SA is in the off state.
When the voltage of one of the pair of bit lines BL and BLX and the pair of extended bit lines RD and RDX drops, the sense amplifier start signal SAE changes to H. At this time, the row selection signal, the precharge signal PRE, and the column signal COL change to H and the equalize signal EQD is maintained at H.
In response to this, the pair of bit lines BL and BLX and the pair of extended bit lines RD and RDX are cut off and the voltage of the pair of bit lines BL and BLX changes to H by the precharge circuit PC. Because the row selection signal changes to L, the memory cell C0 is cut off from the pair of bit lines BL and BLX and maintains a state corresponding to the stored data.
The sense amplifier SA amplifies so that one of the pair of extended bit lines RD and RDX which is on the low voltage side changes to L or is maintained at L and the other on the high voltage side changes to H or is maintained at H. The changed state of the pair of extended bit lines RD and RDX is notified to the output circuit via the column switch. When the output of the state of the pair of extended bit lines RD and RDX to the outside is completed, the sense amplifier start signal SAE changes to L and the sense amplifier SA enters the off state, and the equalize signal EQD changes to L and the equalizer EQ changes the pair of extended bit lines RD and RDX to H.
In the way described above, both the pair of bit lines BL and BLX and the pair of extended bit lines RD and RDX turn to H and a state is brought about where the next read is performed.
The above is the read operation of a general SRAM.
The characteristics of transistors forming memory cells vary in the manufacturing process. By the variations of the characteristics of N-channel transistors of two inverters, the amount of amplitude on the side of the pair of bit lines BL and BLX which changes to L differs considerably. In other words, the speed of the change to L of one of the pair of bit lines BL and BLX differs.
In BL/BLX in FIG. 2, a illustrates the change when the N-channel transistor has favorable characteristics, b illustrates the change when the N-channel transistor has average characteristics, and c illustrates the change when the N-channel transistor has poor characteristics, respectively. Further, in RD/RDX in FIG. 2, d illustrates the change when the N-channel transistor has favorable characteristics, e illustrates the change when the N-channel transistor has average characteristics, and f illustrates the change when the N-channel transistor has poor characteristics, respectively.
In order for the sense amplifier SA to correctly amplify the voltage to L on the side where the voltage of one of the pair of extended bit lines RD and RDX has dropped, it is preferably for the voltage difference between the pair of extended bit lines RD and RDX to be a predetermined amount or more. In the other words, the voltage of the other of the pair of extended bit lines RD and RDX is at H, and therefore, it is preferably for the lower voltage to be a predetermined value or less. There arises no problem when the characteristics of the N-channel transistor are favorable, however, when the characteristics of the N-channel transistor are poor, the sense amplifier start signal SAE does not change to H until the voltage of one of the pair of extended bit lines RD and RDX drops to the predetermined value or less. As a result, the time that the voltage of one of the pair of extended bit lines RD and RDX drops to the predetermined value or less determines the read speed.
As described above, in order to reduce power consumption, the operating voltage is reduced, and therefore, the reduction in read speed appears more remarkably as the operating voltage is reduced. Because of this, it is difficult to sufficiently reduce the operating voltage while maintaining a predetermined operating speed.
Further, in the SRAM, it is preferable to correctly read data stored in all the memory cells and it is preferable to set the read speed in accordance with the memory cell the slowest in operation. If such a read speed is set, when reading data from the memory cell having the transistor with average or favorable characteristics, the transistor of the memory cell changes the voltage of one of the pair of bit lines BL and BLX considerably as a result, i.e., in other words, the amount of amplitude becomes large and power consumption is increased.